Layer 3 ethernet protocol for FPGA based systems

• The FPGA IP core, written in VHDL and tested currently in three platforms:
  • Spartan-6 FPGA SP601 Evaluation Kit
  • Spartan-3E Starter Kit
  • Atlys™ Spartan-6 FPGA Development Board
  The IP core uses the 10 100 1000 Mbps tri-mode Ethernet MAC to communicate with Ethernet PHY.
• The simplified layer 3 network protocol, which uses the unofficial 0xfade Ethernet type frame (as the protocol is used only in small private network consisting of a single segment or a few segments connected via Ethernet switch, use of unofficial Ethernet type should not be a problem)
  The protocol uses only four types of packets:
  • START transmission packet (send to FPGA)
  • STOP transmission packet (sent to FPGA)
  • DATA packet (sent by FPGA)
  • ACK packet (sent to FPGA)
• The Linux kernel driver, which handles reception of the 0xfade type packets, receives the data from the DATA packets and sends the ACK packets. Driver minimize the acknowledge latency, which in turn allows to obtain high transmission speed with small amount of memory in FPGA used to buffer the transmitted, and not confirmed yet, data.
  The received data are exposed to the user space application via circular buffer, which may be memory mapped, to minimize overhead associated with access to the data. Necessary synchronization is assured by the ioctl function, which is used to read and update pointers used by the buffer. Driver may service multiple network cards with one or more (if a switch is used) FPGA boards connected to them.
  Application may sleep waiting for data.

Download

• sources of the first version
• sources of the second, improved version in the zip format or in the tar.bz2 format