Fpgadbg - a tool for FPGA debugging

fpgadbg_core - the signal recorder

entity fpgadbg is
  generic (
    outwidth    : integer := 16;
    width       : integer := 35;
    log2samples : integer := 10);
  port (wr_clk             : in  std_logic;
        trigger         : in  std_logic;
        wr_init             : in  std_logic;
        data_in         : in  std_logic_vector((width-1) downto 0);
        post_tr_samples : in  integer range 0 to 65535;
        triggered       : out std_logic;
        completed       : out std_logic;
        rd_init         : in  std_logic;
        rd_finished     : out std_logic;
        rd_clk          : in  std_logic;
        out_data        : out std_logic_vector((outwidth-1) downto 0)
        );
end fpgadbg;
    

• outwidth - the width of the output port.
• width - the length of the input port, and the width of the debug memory.
• log2samples - this parameters describes the depth of the debug memory. Number of samples is equal to 2**log2samples

• wr_clk - this is the clock used to sample the recorded data
• trigger - this is the trigger used to start the data acquisition
• wr_init - this is the active low reset signal, preparing the fpgadbg to recording of data
• data_in - this is the vector of the recorded signals
• post_tr_samples - this is the amount of samples to be taken after the trigger
• triggered - this output informs if fpgadbg has been triggered
• completed - this output informs if fpgadbg has completed to record the data (i.e. has recorded post_tr_samples after the trigger went high
• rd_init - this input starts the process of receiving data
• rd_finished - this output informs that all data have been succesfully received
• rd_clk - this is the clock used to read the recorded data
• out_data - this is the output of the recorded data. When width > outwidth (the typical situation) a single recorded vector is splitted between a few consecutive output words.

• log2samples - binary logarithm of the maximum number of samples (the real number of acquired samples may be smaller, if the buffer has not been filled completely - e.g. when trigger occured right after initiating of recording, and the post_tr_samples value was small
• width - length of the recorded words. You should use this value to calculate how many output words uses a single sample.
• trig_pos - IMPORTANT! when outwidth is less than 16, this information is transmitted as 2 words. informs on which position in the buffer has the trigger occured.
• stop_pos - IMPORTANT! when outwidth is less than 16, this information is transmitted as 2 words. informs what is the position of the last sample written into the buffer (in fact the trig_pos, stop_pos and post_tr_samples values are correlated, but it was more convenient to have such redundant information in the data record)
• Next words, starting from the 5th (or 7th if the outwidth is less than 16) contain the recorded samples.

fpgadbg_uart

entity fpgadbg_uart is
  generic (
    brg_div     : integer := 50000000/16/115200;
    width       : integer := 35;
    log2samples : integer := 10);
  port (
    wr_clk  : in  std_logic;
    trigger : in  std_logic;
    data_in : in  std_logic_vector((width-1) downto 0);
    rs_rx   : in  std_logic;
    rs_tx   : out std_logic;
    xconf   : out std_logic_vector(2 downto 0);
    sys_clk : in  std_logic;
    nrst    : in  std_logic
    );
end fpgadbg_uart;

• brg_div - divider needed to obtain the UART clock frequency (16x baud rate) from the system clock. Default has been selected for Spartan 3 Starter Board and baud rate 115200.
• wr_clk, trigger, data_in - as in fpgadbg
• rs_rx - UART RX line
• rs_tx - UART TX line
• xconf - additional bits, sent from the PC, which may be used to select one of available configurations.
• sys_clk - system clock
• nrst - reset line (active low)

fpgadbg_conv - the signal converter

assgn=((20,11,"counter_nb"),
   (10,10,"Clk"),
   (9,0,"lsr"))

cnv=fpgadbg_conv.fpgadbg_conv(assgn,16,125,-10,"test.lxt")

• assignments - signal assignment description
• nbits - number of bits in the fpgadbg_core communication interface. In fact it shouldn't be less than 16. Otherwise you can have problems with passing of some values like: trig_pos, stop_pos
• timestep - this should be an integer associated with the sampling clock period. Tsmp=timestep*10^timescale
• timescale - explained above
• filename - Name of the output LXT file

cnv.conv(data)

Description of the sources

• fpgadbg_core
  This directory contains the VHDL sources of the fpgadbg component (fpgadbg.vhd, fpgadbgmem.vhd) which should be connected to your design. Here you can also find sources of the fpgadbg_uart interface (fpgadbg_uart.vhd, smalluart.vhd). In this directory there is also a functional testbench fpgadbg_tb.vhd - used for simulation.
• fpgadbg_conv
  This directory contains the sources of the conversion utilities, which receive the data from the fpgabdg_core, and store it in the LXT file (used by the gtkwave viewer)
  Some of these sources are not written by me, but have been taken from the gtkwave sources (the gtkwave's license allows for it).
  Execute "make" command in this directory to build necessary extension modules.
• demo_sim
  This directory contains a build environment to create a functional demo showing operation of fpgadbg in the simulated environment. To build this demo, execute the "make" command in this directory. (However to do it you'll need the Swig tool and the GHDL compiler and simulator.)
• s3sb
  This directory contains the VHDL sources specific for Spartan 3 Starter Board. They are used to build a demo showing how fpgadbg works in a real hardware.
• demo_s3sb
  This directory contains a build environment to create a working demo of fpgadbgf for Spartan 3 Starter Board. To build this example execute the "make" command in this directory. (However you need the Xilinx tools - e.g. WebPack version 8.2 installed, and XILINX environment variable correctly set; additionally you'll need the XC3Sprog utility, or you should modify makefile to use impact instead)

Old version

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