USB STAPL Player

DISCLAIMER

The USB STAPL Player is a free design. There is no warranty of any kind. It has worked for me, and I tried to avoid mistakes when describing it. However I'm not sure if my description is correct.
Incorrect functioning of the JTAG hardware may lead to destruction of expensive FPGA chips, and probably to other problems. If you decide to use the USB STAPL Player, you will use it on your own responsibility!

Introduction

This page describes the free and open-source USB STAPL Player. This is a device, which you can use to configure your FPGA devices, or to perform some tests via the JTAG interface. The STAPL (JAM) files may be generated by the FPGA synthesis tools, it is also possible to write simple programs. The IDCODE reader provided by Altera may be a good choice for first tests.
The USB STAPL Player consists of two parts - the Modified Altera Jam STAPL Player and the dedicated hardware based on the PIC 18F4550 microcontroler.

Modified Altera Jam STAPL Player

I have modified the original Altera Jam STAPL Player (available from Altera web site), adding the "clustering" of the write operations (as described in my post "Jam STAPL Player extensions for SCANSTA111 and fast transfer via VME/USB" on the alt.sources usenet group, available e.g. here), and the USB support. The USB support is based on the libusb library. My additions to the Altera Jam STAPL Player are licensed under the GPL license, with the additional clause allowing them to be used with the Altera Jam STAPL Player (as it is not clear to me whether the original Altera's license is GPL compatible). The modified sources may be found here.
The modified Jam STAPL Player accepts two additional parameters:

-o: number of the JTAG chain (up to 8 JTAG chains may be used, 2 are available in my simplified hardware)
-t: delay value (used to slow down the generated TCK waveform)

The sample command line when using the Altera's idcode:
$jamplayer -o1 -t0 -aread_idcode idcode.jam
Please note, that if you are going to run the jamplayer from the normal user account, you may need to add a new rule to your udev configuration (on the Linux system).

USB STAPL Player hardware

To simplify the design, I have used the didactical board with PIC18F4550 processor, prepared for our students (schematic diagram available here). The board has only been supplemented with the level converters needed to connect it to the JTAG chains with Vcc lower than 5V (because the PIC18F4550 uses Vcc=5V).
IMPORTANT!!!
Please note, that the Vcc_JTAG nets are local for each JTAG chain. Each chain may work with its own, different Vcc_JTAG voltage. Shortening of Vcc_JTAG between two chains may destroy connected boards (or at least one of them)!

Because the level converters invert the logical signals, it is necessary to set the pin_invert table in the jtag.c file in the PIC firmware.
Two different kinds of voltage converters have been provided. The first one (providing the TCK_PD signal) is well suited for pulled-down TCK lines, which may be found on the Altera development boards. The second one (providing the TCK_PU signal) is well suited for pulled-up TCK lines, which may be found on Xilinx development boards.
The resistors R5, R9, R11 and R14 may be omitted.
The connector of the voltage converters board may be connected either to pins 26-24-22-20-18-16 of the J2 connector on our didactical board (chain 0) or to the pins 25-23-21-19-17-15 of this connector (chain 1).
Certainly you may use other pins, designing your own PCB, and changing the definitions found in the jtag.h file in the firmware sources. Please note, that you will probably need to change the init_jtag function as well, to set the proper mode and direction of the particular pins of the PIC microcontroller.

USB STAPL Player firmware

The USB STAPL Player firmware is based on the the PIC USB Framework written by Pierre Gaufillet. All firmware and software is free and may be compiled with free tools.
Please note, that in the Makefile you'll need to set the TOOLSDIR variable to the full path of your sdcc installation.
The current firmware is prepared by modification of the original bootloader. The original FLASH writing functions have been removed, and the firmware update via USB is impossible. Probably it is also possible to write the firmware as the "PUF application"...

USB ID Disclaimer

Because the USB STAPL Player is a free design, I was not able to obtain the legal vendor id and product id for it. Therefore it uses the bogus values: Vid=0xa5a5, Pid=0x0313. If you are going to distribute and/or sell any device based on it, you will probably need to obtain the legal Vid and Pid. Otherwise you will probably run into legal problems.

Protocol

The USB protocol used on the USB bus a few requests:

code	name	explanation	response	remarks
1100nnnn	BLOCK_DATA_WITH_READ	bits "nnnn" - encode the bits 11...8 of the datastream length, bits 7...0 are located in the next byte. Following bytes are the data to be sent.	11000000 followed by the read TDO data, as described below	not optimized function, currently not used
1011nnnn	BLOCK_DATA	bits "nnnn" - encode the bits 11...8 of the datastream length, bits 7...0 are located in the next byte. Following bytes are the data to be sent.	10110000
1110cccc	SELECT_CHAIN	bits "c" (3..0) - number of the chain. In fact the bit 3 is ignored, as only 8 chains are available.	11100000
1101rcmd	SET_PINS	bit r - TRST (currently not used!!!), bit C - TCK, bit m - TMS, bit d - TDI	11010000	currently not used
101011md	SINGLE_DATA_WITH_READ	bit m - new value of TMS, bit d - new value of TDI	1010110v	"v" is the read TDO value
0x02	CONFIG_CHAIN	The next two bytes encode the delay value	10101100
0x01	GET_INFO	Sends the device identifier	"USB JTAG GPL Interface 1.0"

The block commands accept the sequence of bytes with the data to be sent:
m_{3}d_{3}m_{2}d_{2}m_{1}d_{1}m_{0}d_{0}, m_{7}d_{7}m_{6}d_{6}m_{5}d_{5}m_{4}d_{4} , ....
The block read command returns the received bits as the sequence of bytes:
d_{7}d_{6}d_{5}d_{4}d_{3}d_{2}d_{1}d_{0}, d_{15}d_{14}d_{13}d_{12}d_{11}d_{10}d_{9}d_{8}, ...

Wojciech M. Zabolotny

Last modified: Mon Oct 29 20:20:47 CET 2007